// Cell names have been changed in this file by netl_namemap on Mon Jan  3 04:05:25 UTC 2022
module dwc_e12mp_pads_x4_ns (
  rx0_m,
  rx1_m,
  rx2_m,
  rx3_m,
  rx0_p,
  rx1_p,
  rx2_p,
  rx3_p,
  
  tx0_m,
  tx1_m,
  tx2_m,
  tx3_m,
  tx0_p,
  tx1_p,
  tx2_p,
  tx3_p,
  
  resref,
    
  `ifdef DWC_PMA_PADS_PWRSW
  ana_pwr_en,
  ana_pwr_stable,
  `endif
  
  `ifdef DWC_E12MP_X4NS_PG_PINS
    vp,
    vph,
    gd,
    `ifdef DWC_PMA_PADS_PWRSW
    vp_i,
    `else
    vpdig,
    vptx0,
    vptx1,
    vptx2,
    vptx3,
    `endif
  `endif
  
  ref_pad_clk_m,
  ref_pad_clk_p
);

inout rx0_m;
inout rx1_m;
inout rx2_m;
inout rx3_m;
inout rx0_p;
inout rx1_p;
inout rx2_p;
inout rx3_p;

inout tx0_m;
inout tx1_m;
inout tx2_m;
inout tx3_m;
inout tx0_p;
inout tx1_p;
inout tx2_p;
inout tx3_p;

inout resref;

inout ref_pad_clk_m;
inout ref_pad_clk_p;
  
`ifdef DWC_PMA_PADS_PWRSW
input  ana_pwr_en;
output ana_pwr_stable;
`endif

`ifdef DWC_E12MP_X4NS_PG_PINS
  inout vp;
  inout vph;
  inout gd;
  `ifdef DWC_PMA_PADS_PWRSW
  inout vp_i;
  dwc_e12mp_pads_x4_ns_pads_pwrsw_model pwrsw (
    .ana_pwr_en     (ana_pwr_en),
    .ana_pwr_stable (ana_pwr_stable),
    .vp             (vp),
    .vp_i           (vp_i),
    .gd             (gd)
  );
  `else
  inout vpdig;
  inout vptx0;
  inout vptx1;
  inout vptx2;
  inout vptx3;
  `endif
`else // else: upf-mode or rtl/func-mode
  `ifdef DWC_PMA_PADS_PWRSW
  `ifndef DWC_E12MP_X4NS_UPF_MODE
  // model switch for rtl/func mode
  dwc_e12mp_pads_x4_ns_pads_pwrsw_model pwrsw (
    .ana_pwr_en     (ana_pwr_en),
    .ana_pwr_stable (ana_pwr_stable),
    .vp             (1'b1),
    .vp_i           (),
    .gd             (1'b0)
  );
  `endif
  `endif
`endif

endmodule


`include "dwc_e12mp_phy_x4_ns_macros.v"
`timescale `DWC_E12MP_X4NS_TIMESCALE
module dwc_e12mp_pads_x4_ns_pads_pwrsw_model (
  input  wire ana_pwr_en,
  output wire ana_pwr_stable,
  
  inout  wire vp,
  inout  wire vp_i,
  inout  wire gd
);

real turn_on_delay;
real turn_off_delay;
reg  stable_int;

wire power_good = (vp === 1'b1) && (gd === 1'b0);
wire power_down = (vp === 1'b0) && (gd === 1'b0);

// -------------------------------------------
// Power switch
// -------------------------------------------
assign vp_i = (ana_pwr_en === 1'b1) ? vp : 1'b0;

// -------------------------------------------
// Power stable generation
// -------------------------------------------
initial begin
  turn_on_delay = `PADS_PWRSW_TURNON_TIME;
  turn_off_delay = `PADS_PWRSW_TURNOFF_TIME;
  stable_int = 1'b0;
end

always @(ana_pwr_en) begin
  if (ana_pwr_en) begin
    // apply delay on power-up
    if (~stable_int) begin
      #(turn_on_delay);
      stable_int = ana_pwr_en;
    end
    else begin
      stable_int = 1'b1;
    end
  end
  else begin
    if (stable_int) begin
      #(turn_off_delay);
      stable_int = 1'b0;
    end
    else begin
      stable_int = 1'b0;
    end
  end
end

assign ana_pwr_stable = power_down ? 1'b0 : (power_good ? stable_int : 1'bx);

endmodule

